PWM dead time generator

Not by any means a novel circuit, but nevertheless handy in PWM and SMPS circuits for adding or rather inserting dead time into the PWM signal, so that for example the conduction of the power transistors in a half- or full-bridge does not overlap.

The circuit delays the rising pulse edge by a fixed amount of time. In other words it delays the PWM'ed turn-on signal of the power transistor.

The logic gate is a XOR gate, 74HC86 is fine for 2.0V..5.0V circuits. At 500kHz, a 15pF capacitor and 10kOhm potentiometer or trimmer work fine and give about 0-200ns adjustable delay.


(C) 2006 Jan Wagner