Solid state tesla coils - general notes

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4. Gate drive pulse transformers, design tips and examples

Even though there are various floating channel mosfet/IGBT driver ICs available (IR's IR2110 series, and probably others) a transformer coupled gate drive is still the better option to use for high power solid state TCs, for a multiple of reasons, the most important being that you can quite freely choose the number of galvanically isolated output windings - a single transformer can drive all mosfets in the bridge. In addition, a xfmr with multiple outputs makes it a lot easier to drive parallel mosfets/IGBTs. And, it has negative gate bias i.e. the output goes to -10V (for example). This is extremely helpful in noisy environments like high voltage Tesla coils.

If you don't want to go through the DIY design hassle, you can get 1-2 free gate drive xfmr samples from CoilCraft (www.coilcraft.com, in the "power magnetics" section). These xfmrs are wound on EE instead of toroidal cores but nevertheless work quite well and up to specs (25kHz and higher), and are well suited for larger commercial products.


GDT construction tips:

Transformer core:
The by far most crispy square wave output can be achieved with toroidal ferrite cores, specifically those which are used in RF filtering chokes and broadband transformers. EE- and pot-cores don't perform too well.

The design of gate drive transformers is described in excellent detail in a TI tech seminar paper (see [1] at end of this page). I'd recommend you have a look at it and learn about gate drive techniques. This page here will be easier to understand when you know some more of the background basics.

What the design procedure really boils down to is that the leakage inductance, which causes time delays (phase shift) and ringing in the output signal, must be kept small. To achieve this, the number of turns has to be kept at a minimum. At the same time, a high magnetizing inductance (even with only those few 10 turns per winding) is desired so that the magnetizing current is small.

I_mag = V_drive / (2*pi*f*L_mag)


A higher L_mag decreases the magnetizing current, for a given frequency. This is the current supplied to magnetize the transformer core, and it ramps up and down linearly. It doesn't have any effect on the output signal nor does it restrict the xfmr peak output current. The only effect is that a
I_mag that ramps up too high will cause a noticeable voltage droop (downwards slope) in the output signal. If the droop is less than 1V this is still acceptable, but if it is larger, and - most importantly - if the output signal falls below the MOSFETs minimum gate voltage for saturation (typically 10V) while the MOSFET should be ON, then this xfmr won't work. It will have to be re-designed, with more turns or with a higher permeability core, or a core with a larger cross section.

To sum it up, a good core for making a gate drive transformer is an non-gapped toroidal ferrite core that has a relative permeability ur larger than 4000 and a large A_L value (~diameter), for example more than 1400 nH/(turn^2). In addition, the core should be rated for MHz range use. If you have only cores of unknown type, and no inductance or LCR meter, GDT design will be a painstaking process - I'd really recommend acquiring an LCR meter, even a cheap one will do.


Some practical tips for winding:

- When testing a core, it is easiest to first use only two interwound wires. Don't bother with pri:sec turns ratio right now. Make 40 turns on the core, test the output waveform and driver chip input current draw, reduce turns, test again, and so on, gradually reducing the number of turns to a minumum. Once you find a good minimum number of turns (this is always a compromise), then you can wind the actual transformer. This time with the correct pri:sec turns ratio.

- For more than 2 outputs, interwind each pair of 2 sec wires with 1 pri wire, to get one strang. Make several strangs, enough for the number of required outputs. Bifilarly wind these strangs onto the core, then connect the primary wires in parallel. This seems to be the best way to get a low leakage inductance (=>low output ringing and fast rise and fall times) even for a multiple-output gate drive transformer.

- For a 1:2 (pri:sec) turns ratio, usually required by the single ended drive method where one end of the gate drive xfmr is switched and the other is permanently grounded, AND the secondary side should swing -12V to +12V (instead of 0V to 12V, capacitive coupling plus DC restoration), then the primary wire is only half as long as the secondary. To get the best coupling, use two primary wires along the secondary wire(s), so that there's one primary wire at all points along the secondary wire. Later, after winding this on the core, connect the primaries in parallel. With only one primary wire, well-coupled to only half of the secondary, the leakage inductance will be larger and the transformer output looks worse (of course, you may try the simpler single-pri first, and see if it is still acceptable for your design).


Some reference values for designing the transformer:
Inductance
of the primary
50kHz-100kHz operation between 2.0 mH and 4.0mH
100kHz-300kHz operation between 0.5 mH and 2.0 mH
300kHz-500kHz operation between 50uH and 500uH
Turns at most 30 turns per winding (as a rule of thumb...), less than this is even better
Turns ratio usually 1:1:1, or 1:1.5:1.5
both work for a double-ended 15V or 12V drive circuit, which means that both ends of the gate drive transformer primary are switched (like in a tiny full-bridge)

for a single-ended drive circuit (that is, one end is permanently grounded and only the other end is switched, "half-bridge") a turns ratio of 1:2:2 or 1:2.5:2.5 is required. Winding such a transformer properly gets tricky and the output waveform isn't quite convincing, so I wouldn't really recommend the single-ended drive scheme
Leakage inductance below 4uH (0.004mH) for ~100kHz transformers, and well below 1uH for ~300kHz transformers. Leakage inductace is not easy to measure (needs a uH range inductance meter), but you can trust that it will be "automagically" ok when you use windings with less than ~30 turns.

If you really want to know: the method for measuring leakage inductance is easy. Start by shorting out all the windings which have the highest number of turns. Then measure the inductance of the last (open) winding which has the smallest number of turns. The inductance measured is the leakage inductance. Or very close to it anyway. :o)
Interwinding capacitance in the picofarads range. Again, not so easy to measure, at least not with a cheap multimeter.
DC resistance DC resistance of the primary and other windings is less than 0.5 Ohm
Wire enameled copper wire, teflon insulated wire, other well insulated wire
wire has to be large-diameter enough to achieve a low winding resistance, 0.3mm wire or thinner is ok
Winding style bi/trifilar winding style
the windings should additionally be weaved/twisted together to get a good output pulse shape
Insulation the wire enamel or other insulation should be rated for at least 350V and for high dV/dt. 600VAC is better. A kV rating isn't required.



Testing:

An example test circuit is shown on the right. The main parts are the series coupling capacitor (C1+C2+C3) and the test load (C4).

A good start for the the series coupling capacitor C1 is a 16V foil pulse capacitor of at least 10nF. Better yet, 470nF or 1uF instead of only 10nF. C2 and C3 are two back-to-back 63V or 100V polar electrolytics.

R1 can be a 2,2 Ohm 1W metal foil resistor (not wire wound) for initial testing.

C4 is the test load ("gate capacitance"), a ceramic or foil capacitor of around 10nF.


If the mosfets or IGBTs for the bridge are already chosen, C4 could also be replaced with a capacitor that has the expected gate capacitance, i.e.
    C4 = (Q_g / Vgs_test) * 1.5 * num_transistors
where Q_g and Vgs are found in the transistor's datasheet
    Q_g = maximum value of "total gate charge Q_g"
    Vgs_test = the value of Vgs given next to Q_g in the datasheet
and
    1.5 = safety margin (+50%)
    num_transistors = how many transistors the GDT will drive

As an example, consider driving an H-bridge with IRFP460C MOSFETs. Now, num_transistors = 4. Next, the datasheet for IRFP460C (use www.google.com to find others) states on page 2 under Switching Characteristics: Qg total gate charge (Vds=400V, Id=20A, Vgs=10V) is max 170nC. This gives Q_g=170nC, Vgs_test=10V. Plugging the numbers into the formula above:
    C4 = (170nC/10V)*1.5*4 = 17nF*6 = 102nF
to which the closest standard capacitor would be 100nF. So, a 100nF 63V polypropylene or other pulse cap will do as a test load.

In the schematic, switch S1 is just symbolic. Either one end of the transformer is grounded (single-ended drive style, not recommended) or is connected to a inverted high current drive (double-ended drive) - such that when IC1A output is high then IC2A is low. IC1 and IC2 could be the TC4421 and TC4422 driver ICs, respectively. If the total capacitance of the mosfet or IGBT gates (test load C4) is very large, and fast switching would require more than 6A peak currents, a discrete driver circuit as shown in the half-bridge SSTC schematics may be a viable alternative.

When you switch on the drive circuit you should get a nice and clean square wave on the oscilloscope, similar to the one shown to the right. It should be free of noise and distortion and stay above 12V in a frequency range of at least 100kHz around the intended operating frequency. If there is significant ringing or spikes in the signal, first try a 4,7 Ohm or larger metal foil resistor R1 in series with the test load capacitor.
 
If the the signal looks otherwise ok with steep rising edges but the pulse tops are slowly ramping downwards (called "droop"), this means that either the magnetizing inductance or the coupling capacitor is too small. The first thing to try is add larger electrolytic caps C2 and C3 to the coupling capacitor. If it doesn't help, add more turns to the windings.

If on the other hand the pulse edges (pulse rise, fall) look sloppy, or the signal resembles a triangle/sawtooth wave rather than a square wave, and R1 is already smaller than 1 Ohm, then it seems like the driver circuit is not capable of sufficiently high peak output currents. A possible solution are the TC4422 and TC4421 mosfet drivers with at least 9A peak output current, the cheaper TC4429 with 6A peak out, or a discrete high current driver. It may also be that the leakage inductance, or core losses at this frequency, are unacceptably high - this means you've to try another xfmr core.

If the signal looks like a sine instead of square wave, then there are way too many turns on the windings.

For 300kHz SSTCs a 100ns rise and fall time or shorter should be ok. For around 100kHz, 300ns or shorter. Because the transistors in the SSTC are soft-switched at the loads' zero current transitions, longer times could be acceptable, as they would not increase switching losses that dramatically. But, for soft-switching to occur the SSTC driver would have to be constantly in tune with the TC secondary.
If the signal shows a DC shift - for example, if pulse tops are at +15V and bottoms at -10V - this is caused either by a non-50%-duty cycle drive signal (meaning everything is ok!! nothing to worry about) or a bad drive circuit which doesn't perform equally for on- and off-switching. The latter usually happens when using a single-ended i.e. "half-bridge" / totem pole driving style circuit as the transformer driver. "Upgrading" this to a dual-ended i.e "full-bridge" / dual totem pole driver style (again, using a TC4422 and TC4421 driver pair, or two TC4429 and a NOT-gate, or discretes) will give a better balanced output signal without DC shift.

Should all fail, check that the scope really displays its own .5Vpp 1kHz calibration signal correctly when the probe is at 1/10 attenuation and adjust the probe termination potentiometer if necessary...



Once the gate drive transformer signal looks clean, connect a isolation transformer to a variac/autotransformer, then the SSTC circuit behind the isolation xfmr. The SSTC circuit must be left ungrounded for scope measurements!! Only the oscilloscope must be grounded. A fast ground fault interruptor (GFI) and fast mains fuses in front of the variac are essential safety precautions.

If you have a base drive ferrite transformer / step-up / impedance match type SSTC, leave the matching transformer secondary unconnected. For a direct TC primary coil drive type SSTC, completely disconnect the TC primary.

If at full line voltage the gate drive signal, measured directly on each mosfet's gate and source pins, shows considerable mess, bumps, noise, voltage drops flapping around at 60 Hz etc, then that is just exactly what often happens. As long as the signal doesn't drop below 10V at any time, then you've succeeded in making a well working gate drive transformer and xfmr drive circuit! Who claimed it was simple...


Recommended further reading:


[1] TI tech seminar paper - Design And Application Guide for High Speed MOSFET Gate Drive Circuits (the xfmr drive related infos start on page 31)
http://www-s.ti.com/sc/techlit/slup169.pdf

[2] thedatastream - gate drive transformer design pages (well presented!)
http://thedatastream.4hv.org/gdt_design.html

[3] Dan McCauleys ultrafast gatedrive circuit
http://www.easternvoltageresearch.com/datasheets/ultrafast_gatedrive.pdf
positive drive, uses a reservoir capacitor (has a minor startup delay), works excellently up to a few MHz (or even 30MHz?)

[4] IRF application note 950 - xfmr drive for large duty cycle ratios
http://www.irf.com/technical-info/appnotes/an-950.pdf

[5] Fritz Schlunder, SHEF Systems: High side MOSFET gate drive: the power of well implemented pulse transformers
http://www.itee.uq.edu.au/~elec4400/datashts/gatedrivers/transformer%20isolated%20gate%20drive.pdf
The PDF presents a simple setup that works properly even at extreme duty cycles (1%..99%). The PDF disappears quite often from the net, here is a copy of the essential schematic:


 


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