Solid state tesla coils - general notes
3. PCB Layout
Proper tight PCB layout is one of the key things in SMPS/SSTC design.
PCB boards can be designed with Eagle which is freeware and downloadable at www.cadsoft.de (Linux, Windows). Don't use the autorouter - route manually.
A typical example of autorouter output is shown below. This is one leg of a full- or half-bridge, with three paralleled mosfets, a schottky diode (D1), and an ultrafast diode (D2).
After doing some manual "optimization" for the high current tracks:
(as a side note: those "resistors" are actually jumpers with small ferrite beads
to suppress MHz-range ringing in the gate drive signal)
The bad thing about this layout is the way the mosfet sources are connected together and how the gate drive signal is applied to them. The main problem is that the gate drive signal "ground" lead connects the mosfets via the copper track at the mosfet sources. That same track carries considerable current - the current flowing into the transformer / primary coil.
Here's a simple demo circuit. It could be the lower left leg of a full-bridge:
[Here L1, L2 and L3 are the source pin inductances of the mosfets (package internal and 6mm external). L4 and L5 are the series inductances of the copper track. Drain inductances are omitted for brevity. The demo simulation uses a 100kHz drive signal with 200ns rise and fall times. The interrupted current is about 13A.]
If the driver switches off the mosfets while there still is a large current flowing through the mosfets and that track, the inductance and fast current decay cause a large voltage spike V = L*dI/dt accross the track (L4 + L5) and the mosfet source lead pin and track inductances L1, L2, and L3.
These voltage spikes will appear in the gate<->source voltage of each mosfet, because the drive circuit "ground" does not bypass these track inductances but goes just straight through them.
For the leftmost mosfet M1 the situation is relatively harmless:
but some 1V peak mess is already visible at the 0V where the mosfet should be off. (Ok, these traces are only a simulation... in reality, a scope measurement will show much worse pulse shapes. Sometimes it is quite surprising that the bridge works at all...)
Anyway, the situation is much worse for the rightmost mosfet M3:
The positive voltage spikes partly exceed the fets' threshold voltage and make it conduct slightly. As the upper leg of the full- or half-bridge has already been switched on at this time (actually, a "very long" time ago), the gate signal spikes will cause a small shoot-through current, a "light" short circuit accross the mains, repetetively. The mosfet M3, and all of the mosfets in the upper bridge leg will get hot. Heating up lowers the threshold voltage of M3, so the same amplitude voltage spikes make it conduct even better.
With all those voltage spikes, there will be two interesting mosfet destruction causes: a) gate under- or overvoltage, killing the mosfet and maybe damaging the driver circuit, and b) a repetetive current shoot-through condition, thermal runaway, and thermal failure.
Not even using a negative bias for the gate drive (-15V instead of 0V in the off-state) will help:
If there were antiparallel zeners directly accross the gate and source, limiting the voltage to +-18V, the zeners would dissipate a large amount of power from the voltage spikes and start running very hot. If underrated (<400mW?) they would fail, and then, the mosfet that was protected is the next failure candidate. Yes, explosions can be impressive...
The current of 13A which is interrupted by mosfet turn-off in this demo is very conservative. IRF740 can handle 32A peak, IRFP460 80A peak, and for running a >1kW peak power bridge with an interruptor and the mosfets strained to their power limits (who could resist trying that? ;o), such high peak currents are run of the mill. With the above PCB layout, the mosfet bridge wouldn't survive more than a few microseconds...
One way to correct a few problems in the above layout is to use a separate gate drive for EACH of the paralleled mosfets. That is, a pulse transformer with three well insulated and galvanically isolated secondaries. Or, to be more precise, that should be six secondaries, because the other three should go to the mosfets in the lower leg of the bridge - the transformer coupling will insure that if the any of the two legs is trying to turn on, the other will be turned off (180deg phase shift in the drive signal).
Other improvements might be as shown in this layout:
Using copper traces with as large surface area as possible helps to get the inductance down, so the voltage spikes L*dI/dt are smaller. Additionally, the larger surface means a lower resistance, so heating losses in the copper are lower. "Hatching" the copper tracks helps to make things look neater and more professional, and will make soldering considerably easier.
The top layer of the board is used, so component pins can be cut shorter, reducing pin inductance.
The mosfet drain pins are left unconnected, and the back metal plates (drain) of the packages are used instead. The mosfets are mounted on a non-painted and conductive heatsink, which is connected to the +320V rail.
The gate drives, one for each mosfet, should be soldered immediately to where the gate and source pins exit the mosfet package, and not somewhere on the PCB or the end of the mosfet pins. The two antiparallel 18V zeners per mosfet should be soldered there as well, and not any farther away.
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