Solid state tesla coils - general notes
- Which topology?
- Recommended reading on MOSFETs and magnetics
- PCB layout considerations
- Gate drive - IR2110 series and pulse transformers, design tips
- Why is dead time between switching mosfets not good in SSTCs?
- Pulse generators - 555 vs UC3846, L494, LM3524
- Impedance matching
- Power MOSFET intrinsic body diode (=bipolar transistor) explained
An oscilloscope is mandatory for testing and debugging a solid state TC...
1. Which topology?
Which switch mode power supply (SMPS) topology should one start with? IMHO although the schematic of a full-bridge looks a bit complicated compared to push-pull and half-bridge designs, sticking straight to a full-bridge topology or its smaller version, the half-bridge, is actually well worth the initial extra effort. In the end, there's much less that can go wrong compared to the other topologies (push-pull, forward converter variants, flyback).
The main advantages of a full- or half-bridge are:
a) no excessive voltage swings on the mosfets. This is a major trouble with push-pull, forward converter, and flyback designs where mosfets will fry to no end, or you have big snubber network resistors running red hot. In a full-bridge as well as half-bridge all voltages are clamped to the supply rails and can not exceed the supply voltage. This means that for 220VAC mains, the mosfets can be 400V ones, or 110VAC mains you can use 250V mosfets (recommended: 500V and 300V, respective). Compare this to >=1000V mosfets required for reliable operation in power push-pull or forward converters...
b) if using a ferrite cored step-up transformer, there's almost no danger of running the transformer into saturation due to "not pushing the transformer equally towards the negative and positive direction by the same amount over a few milliseconds" which leads to "a homely buzzing sound coming from the transformer and some occasional puffs of smoke". (also called "volt-seconds imbalance"). This as well is a major problem in push-pull. It may also be a slight problem in half-bridges (despite all those capacitors). In a full-bridge smps the only imbalance is is due to different mosfet channel on-resistances, and is likely to be in the order of only a few volts in the worst case.
c) optimum utilization of the transformer core using only one primary winding, because the full rectified input voltage is applied to the primary. Compare this to the two balanced windings required in push-pull. In a half-bridge only half the supply voltage is applied to the primary. A minor drawback in the full-bridge is that the primary needs twice as many turns as in a half-bridge to prevent core saturation.
d) possibility to drive a TC primary coil directly without using any intermediate step-up transformer or series capacitor - no problems with voltage spikes. The primary needs only one winding (consisting a couple of turns, and being helical rather than the usual flat pan-cake TC primaries). Push-pull would need a center-tapped primary and the switches would have to withstand more than twice the input voltage.
When using a series capacitor on the primary coil, the switching frequency can go down to even DC / 0 Hz without shorting anything out. This is not possible in push-pull, forward converters, or flybacks.
e) high power levels, up to a couple of kW's. Push-pull and forward converters can barely do 500W, with large troubles and much heating.
a) increased complexity - how to drive the gates of the mosfets. The upper mosfets need 350V+15V gate voltage...
b) requires that the internal body diode/bipolar of the power mosfets are disabled - with one schottky and one fast recovery diode, for each leg of the bridge (leg = one corner of the bridge - can be one mosfet, or a few mosfets in parallel). This increases the total cost of the system.
2. Recommended reading - MOSFETs and magnetics
The must-read list:
- TI tech seminar paper - Introduction to Basic Magnetics
- Microsemi - Micronotes 302 - Rectifier reverse switching performance
(explains why the freewheeling diodes should be of ultrafast type)
- TI tech seminar paper - Design and Application Guide for High Speed MOSFET Gate Drive Circuits
Highly recommended! How mosfet switching works, power losses during switching, gate charge calculations, various gate drive schemes, and transformer coupled gate drive explained in detail
- Mosfet and Igbt drivers - theory and applications
SMPS tutorials, FAQs, troubeshooting, ideas, tools
- SMPS topologies http://www.personal.u-net.com/~hills2/electron/smps.htm
- IdeasForDesign interesting ideas http://www.planetee.com/ideas.jsp
- SSTC intro, some SSTC drive methods http://www.misty.com/people/don/sst.html
- some web based calculations http://www.geocities.com/CapeCanaveral/Lab/9643/
- Alan Sharp's page, transformer design tips
- Eagle for PCB & schematics, good parts library www.cadsoft.de
Richie Burnett's SSTC pages:
- solid state TC experiments: http://www.richieburnett.co.uk/sstate.html
- SSTC driver theory (very good!) http://www.richieburnett.co.uk/sstate2.html
- why mosfets fail in SSTC dutyhttp://www.richieburnett.co.uk/mosfail.html
Alan Sharp's SSTC coils:
- more readable version of his old push-pull SSTC schematic at http://www.hills2.u-net.com/tesla/ssmag.htm
MOSFET and design related
(this list is still under construction...)
AWG vs diameter wire table, help on choosing a transformer core, ferrite core material comparison, design formulas, EMI filter design formulas
- Choosing mosfets (this is for motor control actually, but is nice nevertheless) http://homepages.which.net/~paul.hills/SpeedControl/Mosfets.html
- International Rectifier www.irf.com
This is one of the main power mosfet manufacturers, like IRF740, IRF840 and others. Also makes the IR2110/2113 isolated high side mosfet gate drive chips which are gold worth for quick testing/prototyping of a half-bridge, although not reliable enough for the final SSTC model.
Check out these application notes:
AN-978 HV Floating MOS-Gate Driver ICs
AN-944 Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs
DT97-3 Design tip on "Managing Transients in Control IC Driven Power Stages"
AN-931 Paralleling HEXFETs
- Motorola www.mot-sms.com and www.onsemi.com
Check out these application notes:
AN-929 Insuring reliable performance from power MOSFETs
AN-918 Paralleling Power MOSFETs in Switching Applications
3. PCB Layout
Proper, tight PCB layout is one of the key things in SMPS/SSTC design. You should get some PCB layout software (like the Windows and Linux shareware version of Eagle from www.cadsoft.de) to make your PCBs. As always, the autorouter gives lousy results, so manual routing must be done.
Here's what a typical autorouter might spit out for the upper left leg of a full-bridge:
After doing some manual "optimization":
(as a side note: those "resistors" are actually jumpers with small ferrite beads
to suppress MHz-range ringing in the gate drive signal)
The bad thing about this layout is the way the mosfet sources are connected together and how the gate drive signal is applied to them. The main problem being that the gate drive signal "ground" lead connects the mosfets via the copper track at the mosfet sources, which carries considerable current - the current flowing into the transformer / primary coil.
If the driver is in tune with the TC secondary, this doesn't matter much as mosfets are switched at close to zero currents. But often the driver is not in tune, and there can be large currents still flowing at the time the mosfets are about to be turned off. Now as the mosfets turn off with a fast gate drive, the high current flowing in the copper tracks is cut off fast. The tracks have some inductance which will try to resist the current cut-off. The inductance and fast current decay causes a large voltage spike V = L*dI/dt accross the track.
Of course, these spikes also appear along the "ground"/sources copper track. Because this track carries the small signal "ground" of the gate drive, the voltage spikes will appear in the gate<->source voltage of each mosfet.
With all those voltage spikes, there will be two interesting mosfet destruction causes: a) gate overvoltage, killing the mosfet and maybe damaging the driver circuit, and b) a current shoot-through condition (mains supply short circuit). If the gate voltage spike is large enough to make a mosfet conduct but not blow up, this mosfet and the bridge leg that is turned on next will short out the mains and you'll have some more mosfets exploding. If one of the mosfets actually doesn't explode but fails short-circuit, then this means good-bye for all other fets in the bridge, in the order they are turned on.
One way to correct a few problems in the above layout is to use a separate gate drive for EACH of the paralleled mosfets. That is, a pulse transformer with three isolated secondaries (or really six secondaries, as the other three should go to the fets in the lower leg of the bridge).
Other improvements might be as shown in this layout:
Using copper traces with as much surface as possible helps to get the inductance down, so the voltage spikes L*dI/dt are smaller. Additionally, the larger surface means a lower resistance, so heating losses in the copper are lower. "Hatching" the copper tracks helps to make things look neater and more professional, and will make soldering considerably easier.
The top layer of the board is used, so component pins can be cut shorter.
The mosfet drain pins are left unconnected, and the back metal plates (drain) of the packages are used instead. The mosfets are mounted on a non-painted and conductive heatsink, which is connected to the +320V rail.
The gate drives, one for each mosfet, should be soldered immediately to where the gate and source pins exit the mosfet package. The two antiparallel 18V zeners per mosfet should best be placed there as well, and not farther away.
4. Gate drive
internal levelshifting (max 500V or 600V) for switching the upper mosfet, with very short propagation delays (120ns typical)
under-voltage lockout - when the supply voltage drops below ~8V, they turn off the output pulses => mosfet thermal run-away failures less likely
minimum pulse width to turn on, helps against noise
fair current source & sink capability, 2 amps peak, enough for small mosfets or low frequency switching
"simple" to test the bridge at a large range of frequencies and drive signal duty cycles
no galvanic isolation between 320V and 12V sides: after the mosfets blow, there's a good chance the IR2110 and the low-voltage side circuitry will fry too
turn on / off delays and the small peak output current limit the maximum usable frequency
no negative gate drive bias:
the gate drive will be sensitive to noise in the mosfet source leads. Negative bias is possible with some additional small-signal mosfets, but this is really pretty complex and expensive. In a bad PCB layout, the noise alone is enough to blow up the mosfets.
suffers from Vs undershoot, which results in overcharging of the floating channel capacitor, possibly causing overvoltage to the mosfet gates - the chip has only undervoltage, not overvoltage lockout
to resolve Vs undershoot, a huge amount of tinkering is required - see IR2110 application notes. The better alternative is to build a separate 15VDC supply for each floating leg (one for a half-bridge, two for a full-bridge), and not use the bootstrap diode. But, this 15V supply needs series RF chokes and has to withstand a large dV/dt, maybe 320V/2us. Increases complexity and parts count.
Gate drive transformer (GDT):
very cheap, as it is just a ferrite core/toroid and some turns of enameled or teflon insulated copper wire
inherent negative gate bias
multiple isolated secondaries
=> you could drive a complete full-bridge with just one transformer
limited bandwidth: a frequency range of 200kHz is typical before pulse shape degrades
negative bias doubles the peak gate charging current
it will need discrete mosfets or a high current driver IC to drive the primary, as the typical PWM IC output currents (500mA source/sink) are not enough
GDT construction tips:
The by far most crispy square wave output can be achieved with toroidal ferrite core chokes that are used for EMI suppression and RF filtering. EE- and pot-cores don't perform very here.
Because leakage inductance L_lk causes ringing and time delays (both not nice for the gate drive), keeping it at a minimum is important. Because L_lk increases proportionally to N^2, the number turns N should be kept to as few as possible.
At the same time, the magnetizing inductance should be as high as possible so that the magnetizing current [ I_mag = V_drive / (2*pi*f*L_mag) ], which doesn't go to anything useful, is acceptably low. There's a small dilemma with this - the number of turns should be kept to as few as possible so L_lk is low, but on the other hand L_mag should be high and this would require more turns. The only way to achieve a compromise is to use the highest relative permeability ferrite toroid available, with a ur larger than 6000, and a decent toroid core cross-section.
Also, a large cross section and high permeability is equal to a high A_L value, i.e. the larger the A_L value the less turns are required to get a particular L_mag, and less turns means a lower L_lk. A suitable toroid usually looks a bit overkill for these low power levels, but will work much better than a smaller one...
Some reference values for designing:
of the primary
50kHz-100kHz operation between 2.0 mH and 4.0mH 100kHz-300kHz operation between 0.5 mH and 2.0 mH 300kHz-500kHz operation between 50uH and 500uH Turns at most 30 turns per winding, less is better Leakage inductance below 4uH for ~100kHz transformers, and well below 1uH for ~300kHz transformers (not easy to measure, so just trust it to be ok) DC resistance resistance of the primary and other windings is less than 0.5 Ohm Wire enameled copper wire, teflon insulated wire, other well insulated wire
wire thick enough to get a low winding resistance
Winding style bi/trifilar, and the windings can additionally be weaved up/twisted togethe to get a good output pulse shaper
As a test load, connect a small 10nF or similar value ceramic or foil capacitor directly accross one of the secondaries, without zener diodes.
The primary will need a series coupling capacitor, with good high and low freq response. An initial coupling cap for testing can be made with a small >100nF 16V polyprop./polystyr. cap which has an additional >10uF 63V non-polar electrolytic connected in parallel with it. The non-polar electrolytic can also be built from two >22uF 63V standard polar electrolytics ones in series, with the negative terminals hooked together.
Place your oscilloscope probe on the 10nF load capacitor, using 1/10 attenuation on the probe.
Switching on the driver circuit should give you a nice and clean square wave on the oscilloscope, similar to the one shown above. It should be free of noise and distortion and stay above 12V in a frequency range of at least 100kHz around the intended operating frequency. If there is significant ringing or spikes in the signal, first try a 4.7 Ohm resistor in series with the test load capacitor.
If the the signal looks otherwise ok with steep rising edges but the pulse tops are slowly ramping downwards (called "droop"), this means that either the magnetizing inductance or the coupling capacitor is too small. The first thing to try is add a larger electrolytic cap to the coupling capacitor. If it doesn't help, add more turns to the windings.
On the other hand, if the pulse edges (rise, fall) look sloppy, or the signal resembles a triangle/sawtooth wave rather than a square wave, the driver circuit is probably not capable of high enough peak output currents and should be improved. A possible solution are the TC4422 and TC4421 mosfet drivers with at least 9A peak output current, or a discrete high current driver like the one which you can find in the half-bridge SSTC schematics. A ~100ns rise and fall time, or shorter, should be ok for SSTC frequencies below 200kHz. Running a SSTC at >200kHz isn't a good idea anyway, really...
If the signal shows a DC shift - for example, if pulse tops are at +15V and bottoms at -10V - this is caused either by a non-50%-duty cycle (meaning everything is ok!! nothing to worry about) or a bad drive circuit which doesn't perform equally for on- and off-switching. The latter usually happens when using a single-ended i.e. "half-bridge" / totem pole driving style circuit as the transformer driver. "Upgrading" this to a dual-ended i.e "full-bridge" / dual totem pole driver style (as shown in half-bridge SSTC schematics) will give a much better balanced output signal without DC shift.
Should all fail, check that the scope really displays its own .5Vpp 1kHz calibration signal correctly when the probe is at 1/10 attenuation and adjust the probe termination pot if necessary...
Once the gate drive transformer signal looks clean, connect the SSTC to the mains via a variac and isolation transformer (don't connect ground!). The isolation transformer is a must. Connecting order: first, the variac, then the isolation transformer, then your bridge, then plug in the variac to the mains.
If you have a base drive ferrite transformer / step-up / impedance match type SSTC, leave the transformer secondary unconnected. For a direct TC primary coil drive type SSTC, completely disconnect the TC primary.
If, at full line voltage, there is current draw above say 50mA and/or the gate signals show significantly sloppier pulses, then something is wrong and you'll probably have to try a different number of primary and secondary windings on the gate drive transformer(s).
5. Why is extra dead time between switching mosfets not good in SSTCs?
In typical push-pull, half-bridge, and full-bridge SMPS designs it is very desirable to add some extra delay between one mosfet turning off and the next one turning on. This extra time ensures that the first mosfet is really fully off when the other one starts to turn on, so that the accident of two mosfets being on simultaneously, thus shorting out the mains, can not happen.
This extra time is also called "dead time", and is automatically added to the drive signals in SMPS controllers ICs like LM3524, UC3846, and the like.
The ferrite core transformer primary voltage waveform when driving the secondary base at the
TC resonant frequency with a dead time of about 10%.
The above picture shows the effect of dead time on the transformer primary voltage waveform of a SSTC. The "jumps" in the picture occur during the dead time, when all mosfets are off and the primary is not connected to the supply rail(s). I.e. during this time the primary is floating freely (at least for a short instant...)
The jumps in pri voltage are mainly caused by the TC secondary coil. Even though current flow in the primary coil was interrupted by switching off the mosfets, the TC secondary will continue oscillating and feed the transformer secondary winding.
This causes the voltage accross the primary to rise towards the supply rails, until the voltage is high enough (350V peak) to force the freewheeling diodes of the bridge to conduct. When the diodes are conducting, they are hooking up the primary to the supply rails and will support the current flow into the bridge. => the TC secondary is driving the bridge, and there will be conduction losses in the freewheeling diodes (~ V_forward * I_conducted)..
The longer the dead time of the driver IC (or the shorter the drive signal duty cycle), the longer will be the time during which the TC resonantor current that is mirrored to the transformer primary side is flowing through the freew heeling diodes. The current is still sinusoidal, so the longer the dead time or the shorter the duty cycle, the higher the current will be at the instant the mosfets are turned off. This is also the case later as the mosfets are turned on again. This amounts to increased power dissipations in the freewheeling diodes, which can be rather bad unless you use TO-220 packaged diodes which can be mounted on their own heatsinks.
A larger diode conduction current has the bad effect of increasing the reverse recovery time, i.e. turning off of the diodes gets slower.
There's even more trouble ahead, because switching the mosfets off at high currents (hard switching) causes not only higher switching losses and larger voltage spikes in stray inductances, but also nasty high frequency ringing in the bridge and radiated HF power => possible RF interference problems with other equipment. Using close to 50% duty and switching in-tune with the TC secondary i.e. at zero current (soft switching) will minimize spikes L * dI/dt and ringing, so there are almost no RFI problems caused by the bridge.
The final thing to note here is that a longer dead time, which is equivalent to shorter on-times / smaller drive signal duty cycle, will lead to less energy transferred to the secondary per cycle because power isn't applied as long as it could be. Controlling the max power and energy transfer to the load is desireable for regulated switch mode power supplies to restrict output voltage and current and do some other things too, but, for SSTCs, one'd probably want max power transfer and nevermind mosfet current ratings, so this would be a reason more to keep dead time at a minimum and the drive signal close to 50% duty cycle.
6. Pulse generators
The vast majority of SSTC circuits seem to use some expensive PWM IC (pulse-width modulator IC) like L494, LM3524, or UC3846, although they never really use the PWM features - only the oscillator section.
Taking into account the dead time considerations of the previous "chapter" 5, it isn't so adviseable to use switching signals with much less than 50% duty cycle. Running at 50% duty makes the error amplifier and flip-flop sections of the PWM IC unnecessary. But most ICs have built-in dead time and duty cycles >45% can never be achieved.
A simple 555 timer (preferrably the faster cmos versions, t.ex. TLC555) works quite well to replace the expensive PWM ICs and their (unused!) PWM functions.
Another alternative is the very cheap CD4046, which is a phase locked loop IC having also a voltage controlled oscillator (VCO) on board. The oscillator will give out a precision 50% duty cycle signal, and the frequency can be adjusted with the VCO input voltage.
For circu pages
7. Impedance matching
To get maximum power transfer from the SMPS driver to the TC secondary, the driver output impedance must be matched to the TC secondary impedance. These are matched when both impedances are equal. A matched condition also implies that you are then running your SMPS driver at the max power it can handle - at full juice - and you thus are putting maximum power into the TC secondary and streamers.
Of course, the SMPS driver output impedance may be lower than the driven TC secondary. This would mean that you are running the SMPS at lower/"safer" power levels, i.e. below the absolute maximum rating.
When using a ferrite cored transformer to step up the mains voltage and feed this into the secondary base, the transformer turns ratio between secondary and primary can be used to match the SMPS and TC secondary impedances: the base impedance of the TC Z_sec will be reflected to the transformer primary side as an impedance equal to:
Z_sec_reflected = Z_sec * (N_pri/N_sec)^2
and now your remaining task is to match Z_sec_reflected to the SMPS output impedance.
The SMPS driver output impedance is nothing else but the input voltage divided by the primary coil current at which your driver current limiting scheme (pulse width limiting and/or pulse blanking) will not yet start to act and/or the power transistors won't start blowing up. In terms of primary side power and voltage, the driver output impedance is
Z_driver_out = (V_pri)^2 / P_pri
With this info, you can build the transformer. First a suitable core must be chosen, t.ex. using some transformer ferrite core lookup tables. The core should be rated for the desired power (or a bit more) at the desired frequency. Then the minimum number of turns on the primary can be calculated from the design sheet. Measure the TC secondary input impedance (at the resonant freq of course), and calculate the necessary base feed voltage from
V_sec = SQRT ( Z_sec * P_sec ) ~= SQRT ( Z_sec * P_pri )
at which the TC secondary draws the desired power. The ratio (V_pri / V_sec) then leads to the required turns ratio on the transformer. Adding some more turns to the secondary won't do any harm.
The clearest way to state all this is that you design the transformer turns ratio for a given output voltage. The initial base impedance of the TC secondary is somewhat constant, so that the initial power draw will be P = U_xfmr_sec^2 / Z_tc_sec.
Because the base impedance can only increase from this value (due to streamer loading as well as detuning) this power is also the maximum power drawn. With a specific transformer turns ratio you get out the desired voltage and thus can set the max power.
The same ideas apply to the direct TC primary coil drive method. In this case it is the turns ratio between the air-core primary coil and the TC secondary, as well as the coupling between these two coils, which both determine the size of the TC secondary impedance that is seen by the driver circuit. When increasing the number of pri turns, the impedance seen at the pri side drops down, approaching the impedance of the secondary, thus increasing power draw. Tighter coupling has a similar effect.
Once again, "impedance matching" isn't anything else but choosing the pri turns and coupling in such a way that the power draw doesn't exceed the maximum power your bridge SMPS (mosfet and diodes) can handle, and without going into overcurrent protection mode or to reducing driver pulse width.
In a sense, this "impedance matching" isn't really one of the ordinary impedance matchings, because the impedance of the SMPS primary side is the impedance of the live mains supply. And the mains impedance is quite low, as you can see when shorting out the live wire to neutral... ;o)
Shutting down the mosfets when overcurrent conditions occur does simulates a higher impedance. However, shutting down does not stop current flow. The TC secondary will source current even though the mosfets in the bridge are turned off - this current is conducted by the freewheeling diodes of the bridge, and will flow untics, and it might be in the middle of turning off when the opposite mosfet in the bridge already starts to turn on, so this diode will place a short-circuit accross the mains for a short time before the diode is forced fully off.
But, you should note that this intrinsic "diode" is actually a NPN bipolar transistor. It acts like a diode because the MOSFETs source metallization is shorting the base of this transistor to its emitter, so we basically end up with only the base<->collector junction, which forms a diode.
The main trouble is that a high reverse turn-off current on this diode, especially at a low drain-source voltage on the mosfet, can cause significant charge to accumulate on the base-emitter junction, thus fully turning on the bipolar transistor at a time when it really should be off. This is not very nice, because if the opposing mosfet in the bridge is turned on at the same time, the first mosfet's intrinsic transistor and the next mosfet will place a short circuit accross the mains. More current flows, and the intrinsic biploar transistor will start conducting even better. At some point, probably both mosfets will blow up.
To prevent this from happening, the intrinsic "diode" must be disabled and replaced with a "real" fast recovery diode.